SC|05 SC|05 Gateway to Discovery
About Interactive Schedule Programs Registration Exhibits Initiatives & Challenges News & Press Hotel & Travel




You currently have 0 events on your schedule.

Schedule: November 12-18th 2005
Entire WeekSaturdaySundayMondayTuesdayWednesdayThursdayFriday

HPC Challenge v1.x Benchmark Suite

Session: S13: HPC Challenge v1.x Benchmark Suite

Event Type: Tutorial

Time: 1:30pm - 5:00pm

Speaker(s): David Koester, Piotr Luszczek

Location: 615-616

Abstract:

The HPC Challenge v1.x suite of benchmarks examines the performance of HPC architectures using kernels with memory access patterns more challenging than those of the High Performance Linpack (HPL) benchmark. HPC Challenge is intended to augment the Top500 list and bound the performance of real applications as a function of memory access characteristics. HPC Challenge has been released by the DARPA High Productivity Computing Systems (HPCS) program to define the performance boundaries of HPC architectures. The suite is composed of several well known computational kernels (STREAM, High Performance Linpack, matrix multiply – DGEMM, parallel matrix transpose – PTRANS, FFT, RandomAccess, and bandwidth/latency tests). This tutorial will introduce attendees to the HPC Challenge benchmarks and the unified HPC Challenge framework, provide the tools to examine differences in HPC architectures, and provide hands-on training to equip attendees to run the benchmark suite and develop optimized component kernels in different programming languages and parallel environments.

Introductory: 30% Intermediate: 40% Advanced: 30%



Chair/Speaker Details:

David Koester
The MITRE Corporation

Piotr Luszczek
U of Tennessee